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data sheet (v2) 2005 mar 01 to improve design and/or performance, avant electronics may make changes to its products. please contact avant electronics for the latest versions of its products d a t a sh eet SBN6400G 64-common driver for dot-matrix stn lcd
2005 mar 01 2 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 1general 1.1 description the SBN6400G is a 64-common driver, designed to be paired with the sbn0064g 64-segment driver to drive a dot-matrix stn lcd panel. functionally, the SBN6400G includes 64 co mmon drivers, on-chip rc oscillator, a 64-bit bi-directional shift register, and timing generation circuit. the rc os cillator needs only an external resist or and capacitor. the timing generation circuit generates clocks and di splay control signals for both the SBN6400G and the sbn0064g. to expand common number, the SBN6400G can be cascaded in master-slave connection. 1.2 features ? to be paired with the sbn 0064g 64-segment driver. ? 64-common stn lcd drivers. ? master mode and slave mode for cascaded connection to expand common numbers. ? on-chip rc oscillator; only an external resistor and an external capacitor are needed. ? provides clocks and display c ontrol signal to the sbn0064g. ? external lcd bias (v0, v1, v4, v5). ? selectable display duty cycle: 1/48, 1/64, 1/96, 1/128. ? operating voltage range (v dd ): 2.7 ~ 5.5 volts. ? lcd bias voltage (v lcd =v dd - v5, the voltage added to the lcd cell): 13 volts (max). ? negative power supply (v neg =v dd -v ee ): 16 volts (max). ? operating frequency range: 550 khz. ? operating temperature range: -20 to +75 c. ? storage temperature range: -55 to +125 c.
2005 mar 01 3 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 1.3 ordering information table 1 ordering information product type description SBN6400G-lqfpg lqfp100 pb-free package. SBN6400G-qfpg qfp100 pb-free package. SBN6400G-lqfp lqfp100 general package. SBN6400G-qfp qfp100 general package. SBN6400G-d tested die.
2005 mar 01 4 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 2 functional block diagram and description 2.1 functional block diagram v5r v4r v1r v0r m cl frm clk1 clk2 v ee1 v dd v ss fig.1 functional block diagram 64-bit, bi-directional shift register common shift direction, on-chip rc oscillator c r cr ds1 ds2 timing generation m/s v5l v4l v1l v0l com63 com62 com1 com0 fs dio1 shl psel phase selection dio2 64 high voltage circuit 64-bits level shifter v ee2 64-bits output drive r circuit
2005 mar 01 5 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 3 pin(pad) assignment, pad coordinates, signal description 3.1 the SBN6400G pinning di agram (lqfp100 or qfp100) fig.2 pin assignment of lqfp100/qfp100 package. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 com20 com19 com17 com15 com13 com12 com10 com9 com7 com4 com3 com2 com1 com0 com18 com16 com14 com11 com8 com5 com6 vee1 v1l v4l v5l v0l vdd dio1 fs com21 com43 com44 com46 com48 com50 com51 com53 com54 com56 com59 com60 com61 com62 com63 com45 com47 com49 com52 com55 com58 com57 vee2 v1r v4r v5r v0r nc cl nc com42 dio2 psel nc m frm nc clk1 clk2 m/s nc vss shl nc cr nc r nc c ds2 ds1 com41 com40 com37 com39 com33 com32 com31 com34 com36 com38 com35 com30 com29 com28 com27 com26 com24 com23 com22 com25 SBN6400G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
2005 mar 01 6 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 3.2 the SBN6400G pad placement psel cl 45 31 32 33 34 35 36 37 38 39 40 41 42 43 v1r v0l v5l 72 73 74 75 76 77 78 79 80 81 82 83 84 85 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 com31 com30 com29 com28 com27 com26 com25 com24 com23 87 88 89 90 86 91 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 52 51 50 49 61 com43 com44 com45 com46 com47 com48 com49 com51 com50 com52 com53 com54 com55 com57 com56 com58 com59 com60 com61 com62 com63 v ee2 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 13 com20 com19 com18 com17 com16 com15 com14 com13 com12 com10 com11 com9 com8 com7 com6 com4 com5 com3 com2 com1 com0 v ee1 v1l v4l 26 27 (0,0) x y chip size : 3999 m x 3799 m. pad size: 90 m x 90 m. 47 v5r v4r 48 chip id fig.3 the pad placement note: (1) the total of pad number is 92. (2) the chip id is located at the right middle part of the chip. (3) the chip id is 12001. (4) the die origin is at the center of the chip. (5) for chip_on_board bonding, chip carrier should be connected to vdd or left open. chip carrier is the metal pad to which the die is attached. com22 com21 92 1 28 29 30 3999 m 3799 m ds1 ds2 c r cr shl v ss m/s clk2 clk1 frm m dio2 v dd dio1 fs 44 46 v0r pad #1
2005 mar 01 7 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 3.3 pad coordinates table 2 the pad coordinates (unit: m) pad no. pad name xy pad no. pad name xy pad no. pad name xy 1 com21 1866 1575 35 cr -1857 305 69 com45 1399 -1767 2 com20 1659 1768 36 shl -1857 163 70 com44 1529 -1767 3 com19 1529 1768 37 v ss -1857 20 71 com43 1659 -1767 4 com18 1399 1768 38 m/s -1857 -130 72 com42 1866 -1575 5 com17 1269 1768 39 clk2 -1857 -379 73 com41 1866 -1425 6 com16 1139 1768 40 clk1 -1857 -625 74 com40 1866 -1275 7 com15 1009 1768 41 frm -1857 -873 75 com39 1866 -1125 8 com14 879 1768 42 m -1857 -1052 76 com38 1866 -974 9 com13 749 1768 43 psel -1857 -1276 77 com37 1866 -824 10 com12 619 1768 44 dio2 -1857 -1558 78 com36 1866 -674 11 com11 489 1768 45 cl -1857 -1748 79 com35 1866 -524 12 com10 359 1768 46 v0r -1591 -1767 80 com34 1866 -374 13 com9 229 1768 47 v5r -1461 -1767 81 com33 1866 -224 14 com8 99 1768 48 v4r -1331 -1767 82 com32 1866 -74 15 com7 -31 1768 49 v1r -1201 -1767 83 com31 1866 76 16 com6 -161 1768 50 v ee2 -1071 -1767 84 com30 1866 226 17 com5 -291 1768 51 com63 -941 -1767 85 com29 1866 376 18 com4 -421 1768 52 com62 -811 -1767 86 com28 1866 525 19 com3 -551 1768 53 com61 -681 -1767 87 com27 1866 675 20 com2 -681 1768 54 com60 -551 -1767 88 com26 1866 825 21 com1 -811 1768 55 com59 -421 -1767 89 com25 1866 975 22 com0 -941 1768 56 com58 -291 -1767 90 com24 1866 1125 23 v ee1 -1071 1768 57 com57 -161 -1767 91 com23 1866 1275 24 v1l -1201 1768 58 com56 -31 -1767 92 com22 1866 1425 25 v4l -1331 1768 59 com55 99 -1767 26 v5l -1461 1768 60 com54 229 -1767 27 v0l -1591 1768 61 com53 359 -1767 28 v dd -1838 1785 62 com52 489 -1767 29 dio1 -1857 1533 63 com51 619 -1767 30 fs -1857 1345 64 com50 749 -1767 31 ds1 -1857 1165 65 com49 879 -1767 32 ds2 -1857 984 66 com48 1009 -1767 33 c -1857 776 67 com47 1139 -1767 34 r -1852 601 68 com46 1269 -1767
2005 mar 01 8 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 3.4 signal description table 3 pin signal description to avoid a latch-up effect at power-on: v ss ? 0.5 v < voltage at any pin at any time < v dd +0.5v. pin number pad number symbol description 1~22, 59~100 1~22, 51~92 com21~0 com63~22 common outputs. the output voltage level of common output s are decided by the combination of the alternating frame signal (m) and the in ternal shift register output. depending on the value of m and the shift register output, a single voltage level is selected from v0, v1, v4, or v5 for common driver, as shown in fig. 4. 23, 58 23, 50 v ee1 , v ee2 external negative power supply for lcd bias. these two inputs are internally connected together inside the chip. however, to avoid flickering, same external negative bi as voltage should be connected to these two inputs. 24, 25, 26, 27 24, 25, 26, 27 v1l, v4l, v5l v0l external lcd bias voltage. these pins should be connected to v1, v4, v5, and v dd , respectively, of the external lcd bias circ uit, and the condition vdd v1 v2 v3 v4 v5 must always be met. these pins are internally connected to v1r, v4r, v5r, and v0r, respectively. 28 28 v dd power supply for logic circuit of the chip. the v dd should be in the range from 2.7 volts to 5.5 volts. 29, 50 29, 44 dio1, dio2 input or output for master/slave mode operation in a cascading connection. please refer to sections 4.6 and 4.7. 30 30 fs oscillator frequency selection. when the device operates in master mode, fs is used to select the rc oscillator frequency to make frame frequency approximately equal to 70hz. if the rc oscillator frequency is 550k hz (at v dd =5 volts), then this input should be connected to v dd . if the rc oscillator frequency is 225k hz (at v dd =5 volts), then this input should be connected to v ss. usually, 550k hz is recommended and this pin should be connected to v dd . when the device operates in slave mode, this input should be connected to v dd . 0 1 0 1 0 1 0 1 0 1 0 1 0 v1 v0 v4 v5 v1 v0 v4 v5 fig.4 common output voltage level m com output internal shift register
2005 mar 01 9 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 31, 32 31, 32 ds1, ds2 display duty selection inputs. these two inputs are used to select display duty cycle when the SBN6400G operates in master mode. these pins are not valid in slave mode and should be connected to v dd . 33, 35, 37 33, 34, 35 c, r, cr pins of the on-chip rc oscillator for c onnection to external resistor and capacitor. when operating in slave mode, the device?s c and r terminals should be left open and its cr terminal should be connected to v dd . instead of the rc oscillator, if an external clock source is to be used, then this clock source should be added to the cr terminal. in this case, both the c and r terminals should be left open. 39 36 shl this input is used to select common output sequence when shl=1, common output sequenc e is from com0 to com63. when shl=0, common output sequenc e is from com63 to com0. 40 37 v ss ground. 42 38 m/s this input is used to select master mode or slave mode. when this input is connected to v dd , the SBN6400G operates in master mode. when this input is connected to v ss , the SBN6400G operates in slave mode. 43, 44 39, 40 clk2, clk1 clock outputs to the sbn0064g. the frequency of these two clocks is a half of the rc oscill ator clock frequency. 46 41 frm frame signal, indicating the start of a frame. when the SBN6400G operates in mast er mode, its frm output should be connected to the frm input of the sbn0064g. when the SBN6400G operates in slave mode, its frm output should be left open. for the timing of this signal, please refer to fig. 11 47 42 m alternating frame signal for generating lcd biases of reverse polarites. this is an i/o terminal. when the SBN6400G operates in master mode, this terminal becomes output and should be connected to its slave. when the device operates in slave mode, this terminal becomes input and accepts m output from its master. 49 43 psel phase selection for common output. this input selects the phase relation between the common outputs and the cl clock. if psel=1 (i.e., connected to v dd ), each common output starts on the rising edge of cl. if psel=0 (i.e., connected to v ss ), each common output starts on the falling edge of cl. usually, psel should be connected to v dd . pin number pad number symbol description
2005 mar 01 10 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 52 45 cl shift clock for the internal 64-bi t, bi-directional shift register. the time duration of each common output is equal to one clock period of the cl clock. 54, 55, 56, 57 46, 47, 48, 49 v0r, v5r, v4r, v1r external lcd bias voltage. these terminals should be connected to v1, v4, v5, and v dd , respectively, of the external lcd bias circ uit, and the condition vdd v1 v2 v3 v4 v5 must always be met. these terminals are internally connected to v1l, v4l, v5l, and v0l, respectively. 34, 36, 38, 41, 45, 48, 51, 53 nc no connection. for package type, these pins should be left open. for die, there is no nc pad. pin number pad number symbol description
2005 mar 01 11 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 4 functional description 4.1 on-chip rc oscillator when operating in master mode, the SBN6400G ?s on-chip rc-type oscillator is used to provide clocks and necessary control signals to itself, its slav e, and the sbn0064g segment driver. external resistor r f and capacitor c f need to be connected across r, cr, and c, as shown in fig. 5. the recommended value for r f is 33k ohm and that for c f is 20 pf. during pcb layout, the resist or and the capacitor should be placed as close to the SBN6400G as possible, such that stray capacitance, inductance, and resistance can be minimized. the typical oscillation frequency of the oscillator at different power supply voltages, with c f fixed to 20 pf, is given in table 4. table 4 on-chip rc oscillator characteristics, c f = 20 pf, t amb = ?2 0to+75 c note: 1. the values given in this table are typical values. 10% variation from lot to lot may exists. r f value (unit: ohm) vdd=5v vdd=3v vdd=2.7v unit 47k 406 361 350 khz 43k 443 392 377 39k 484 425 406 33k 557 485 463 30k 601 521 497 fig.5 on-chip rc oscillator cr clk r f vss vdd vss vdd vss vdd c r c f 33k 20p note: (1) when operating in slave mode, the c and r terminals should be left open and the cr terminal should be connected to v dd . (2) when operating in master mode and using an external clock source, the c and r terminals should be left open and external clock source should be added to the cr terminal.
2005 mar 01 12 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 4.2 rc-oscillator frequency selection (fs) when the rc oscillator frequency is 550 khz, fs should be connected to v dd . when the rc oscillator frequency is below 300 khz, fs should be connected to v ss . in the both cases, the purpose of this input is to make frame frequency approximately equal to 70 hz. usually, 550 khz operation is recommended. 4.3 timing generation the SBN6400G?s internal timing generat ion circuit is shown in fig. 6. when m/s =1, the SBN6400G operates in master mode, sends m and cl to its slave, and sends m, cl, frm, clk1, and clk2 to the sbn0064g. when m/s =0, the SBN6400G operates in slave mode and receiv es m and cl from its ma ster. in addition, when operating in slave mode, the SBN6400G will not send out frm, clk1, and clk2. these terminals should be left open. 4.4 duty selection when the SBN6400G operates in master mode, the displa y duty is decided by its ds1 and ds2 inputs. when the SBN6400G operates in slave mode, its ds1 and ds2 has no function and should be connected to v dd . table 5 gives the setting of the ds1 and ds2 and the corresponding display duty cycle. table 5 duty selection ds1 ds2 duty 1 1 1/128 1 0 1/96 0 1 1/64 0 0 1/48 fig.6 timing generation circuit c r cr rc oscillator timing generation circuit ds1 ds2 m/s fs frm clk1 clk2 m cl to internal logic circuit (basic clock) to slave / from master to sbn0064g from external pins(pads) clk note: (1) if fs=1, then clk clock will be divided by 2 inside the timing generator circuit. cl m
2005 mar 01 13 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 4.5 phase relation between cl and common outputs the psel input is used to select the phase relation between cl clock and common outputs. t he cl clock is the shift clock to the internal 64-bit, bi-directional shift register. a cl clock period is t he time duration for displaying a horizontal line of lcd pixels. if psel=h, the com0 starts fr om the rising edge of cl clock. if psel=l, t hen com0 starts from the falling edge of cl, as shown in fig. 7. usually, it is recommended that psel be connected to v dd . fig.7 phase relation between common and cl, as decided by psel 0 1 2 61 62 63 0 1 2 61 62 63 com0 scan period com1 scan period com2 scan period com0 scan period com1 scan period com2 scan period psel=h psel=l cl com0 com1 com2 com0 com1 com2
2005 mar 01 14 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 4.6 master/slave connection the SBN6400G can be cascaded in master-slave connection to expand the total number of commons. when a device is selected as master, its dio1, dio2, m, and cl are all in output state. its m output and cl output should be connected to its slave and its m, cl, frm, clk1 and clk2 should be connected to the sbn0064g. 4.7 common output sequence the common output sequence is decided by both the m/s and the shl inputs, as shown in table 6. table 6 common output sequence in master-slave connection notes 1. when the SBN6400G is in master mode, both its di o1 and dio2 are always output, and common output sequence is decided by shl. if shl=1, com0 is output first and com63 is output last. if shl=0, com63 is output first and com0 is output last. 2. when the SBN6400G operates in slave mode and its shl is high, its dio1 becomes i nput and its dio2 becomes output. the slave?s dio1 should be connected to dio2 of the master. the com0 of the mast er is output first. after com63 of the master is output, com0 of the slav e is output. com63 of the slave is output last. 3. when the SBN6400G operates in slave mode and its shl is low, its dio1 becomes output and its dio2 becomes input. the slave?s dio2 should be connect ed to dio1 of the master. the com63 of the master is output first. after com0 of the master is output, com63 of the slav e is output. com0 of the slave is output last. m/s shl dio1 dio2 common shift direction n otes 1 (master) 1 x output c0 c63 note 1 0 output x c63 c0 0 (slave) 1 input output c0 c63(master), c0 c63(slave) note 2 0 output input c63 c0(master), c63 c0(slave) note 3 fig.8 master/slave connection with shl=1 SBN6400G dio1 dio2 m/s shl master SBN6400G dio1 dio2 m/s shl slave v dd v ss com64 ~~ com127 com0 ~~~ com63 open to next stage or open com0 com63 com0 com63 cl cl m m frm clk1 clk2 frm clk1 clk2 to sbn0064g open to sbn0064g
2005 mar 01 15 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 5 lcd bias and common output voltage 5.1 lcd bias circuit a typical lcd bias circuit for 1/64 display duty is shown in fig. 9. the condition v dd v1 v2 v3 v4 v5 must always be met. the maximum allowed voltage for lcd bias (v dd -v 5 ) is 13 volts. note that v0 should be connected to v dd . 5.2 relation of display duty, cl period, lcd bias, and recommended r esistor ladder for bias table 7gives the relation of display duty, cl peri od, lcd bias, and recommended resistor ladder for bias. table 7 relation of display duty and lcd bias note: 1. when the display duty cycle 1/64 is chosen, the condition should be met. we choose r1=2.2k ohm and, therefore, the calc ulated value of r2 is 11k ohm. as 11k ohm is not a standard value for resistors, we choose a 10k ohm resistor for r1. 2. the duration (period) of a cl clock is a multiple of the clk2 clock. the time duration of each common output is equal to one period of the cl clock. duty cl period bias resistor ladder 1/48 64 x clk2 1/8 r2= 4 x r1 1/64 48 x clk2 1/9 r2= 5 x r1 1/96 32 x clk2 1/11 r2= 7 x r1 1/128 24 x clk2 1/12 r2= 8 x r1 v0l/v0r v1r/v1l v4r/v4l v5r/v5l v ss v dd v0 v1 v2 v3 v4 v5 v dd v dd v ee com0~com63 c c c c c fig.9 lcd bias circui t for 1/64 display duty c omponent r ecommended v alue c 0.1 f, electrolytic r1 2.2k ohm r2 10k ohm r3 10k ohm, variable resistor r1 r1 r1 r1 r2 r3 to sbn0064g to sbn0064g SBN6400G note: (1) v0 should always be connected to v dd . (2) for cascading application, it is recommended that a buffer be added for each of v1, v2, v3, v4, and v5. for 64 com x 64 seg application, these buffers are not needed. (3) the lcd bias voltage (v lcd = v0 - v5) should not exceed 13 volts, without regard to display duty. (4) t he voltage difference between v dd (the most positve power) and v ee (the most negative power), v dd -v ee , should not exceeds 16 volts, without regards to display duty. v ee1, v ee2 r1 () 4r1 r2 + () ? 19 ? =
2005 mar 01 16 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 5.3 common, segment output voltage table 8 gives the output voltage leve l of the SBN6400G common driver and the sbn0064g segment driver. the common output voltage level of the SBN6400G common driver is decided by the combination of the alternating lcd bias voltage (m) and its inte rnal shift register output. the segment output voltage level of the sbn0064g segment dr iver is decided by the comb ination of the alternating lcd bias voltage (m) and the output of its on-chip display data memory. table 8 common/segment output voltage level note: 1. ?data? in the ?data/com? column means the data output from the on-chips display data ram of the sbn0064g segment driver, and ?com? means the output of the SBN6400G?s internal shift register output, which sequentially activates com0~com63. 2. the column display on/off is applicable only to the sbn0064g. frame (m) data/com display on/off seg0~seg63 (sbn0064g) com0~com63 (SBN6400G) l l on v2 v1 l h on v0 v5 h l on v3 v4 h h on v5 v0 x(don?t care) x(don?t care) off v2, v3 x
2005 mar 01 17 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 6 system configuratio n with the sbn0064g table 9 gives examples of system configuration with the sbn0064g. table 9 examples of system confi guration with the sbn0064g. configuration description one SBN6400G drives the com 0 ~ 63 of the panel and supplies timing and display control signals m, cl, frm, clk1, and clk2 to one sbn0064g, which interfaces with a host microcontroller and drives seg 0 ~ 63. one SBN6400G drives the com 0 ~ 63 of both the upper panel and the lower panel, and supplies timing and display control signals m, cl, frm, clk1, and clk2 to two sbn0064g. the two sbn0064g respectively interfaces with the host microcontroller and drives seg 0 ~ 63 of the upper panel and the lower panel. com0 com63 seg0 seg63 SBN6400G sbn0064g 64 x 64 panel m, cl, frm, clk1, clk2 com0 com63 seg0 seg63 SBN6400G sbn0064g 64 x 64 panel m, cl, frm, clk1, clk2 com0 com63 sbn0064g upper panel lower panel seg63 seg0 64 x 64 panel
2005 mar 01 18 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics one SBN6400G operates in master mode and supplies timing and display control signals to two sbn0064g. one SBN6400G operates in slave mode and receives m and cl signals from the master. configuration description com0 com63 seg0 seg63 SBN6400G sbn0064g 64 x 64 panel m, cl, frm, clk1, clk2 com0 com63 sbn0064g upper panel lower panel seg63 seg0 64 x 64 panel SBN6400G m, cl master slave
2005 mar 01 19 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 7 application example 1: master mode, 1/64 display duty 7.1 application circuit for 1/64 disp lay duty, master mode operation fig.10 application circuit for 1/64 display duty, master mode operation m cl frm clk1 clk2 m cl frm clk1 clk2 seg0 seg63 com0 com63 com0 com63 seg0 seg63 shl ds1 ds2 fs m/s psel dio1 dio2 v dd v ss v dd open open v0l, v0r v1l, v1r v4l, v4r v5l, v5r lcd bias circuit v0,v1,v2,v3,v4,v5 v dd v dd v ss v ee v ee v ee v0, v2, v3, v5 sbn0064 SBN6400G microcontroller interface to / from microcontroller 64 com x 64 seg lcd panel v dd v ss v dd r f 33k c f 20p c cr r
2005 mar 01 20 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 7.2 timing diagram of master mode, 1/64 display duty cycle(ds1= l, ds2=h, shl=h(l), psel=h) fig.11 master mode timing for 1/64 display duty 12 0 61 62 63 0 1 2 61 62 63 cl m dio1 (dio2) c0 (c63) c1 (c62) c62 (c1) c63 (c0) dio2 (dio1) v0 v0 v0 v0 v0 v4 v4 v4 v4 v4 v4 v4 v4 v4 v5 v5 v5 v5 v5 v1 v1 v1 v1 v1 v1 v1 v1 v1 frm t cl 01234 92939495 91 note: (1) clk is the clock from the rc-oscillator. (2) the frequency of both clk1 and clk2 is a half of the clk. t cl clk clk1 clk2 01 47 46 1 frame 1frame (input of slave) (output)
2005 mar 01 21 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 8 application example 2: ma ster mode, 1/128 display duty 8.1 application circuit for 1/128 disp lay duty, master mode operation fig.12 application circuit for 1/128 display duty, master mode operation m cl frm clk1 clk2 m cl frm clk1 clk2 seg0 seg63 com0 com63 com0 com63 seg0 seg63 shl ds1 ds2 fs m/s psel dio1 dio2 v dd v ss v dd open lcd bias circuit v0, v1, v2, v3, v4, v5 v dd v dd v ss v ee v ee v ee v0, v2, v3, v5 sbn0064 SBN6400G microcontroller interface to/from microcontroller 128comx64seg lcd panel v dd v ss v dd m cl frm clk1 clk2 shl ds1 ds2 fs m/s psel dio1 dio2 v dd v ss v0l, v0r v1l, v1r v4l, v4r v5l, v5r v ee SBN6400G com0 com63 com64 com127 r f 33k c f 20p c cr r master slave open c cr r open open open open open v0l, v0r v1l, v1r v4l, v4r v5l, v5r
2005 mar 01 22 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 8.2 timing diagram of master mode, 1/128 displ ay duty cycle(ds1=h, ds2=h, shl=h(l), psel=h) fig.13 master mode timing for 1/128 display duty 12 0 125 126 127 0 1 2 125 126 127 cl m dio1 (dio2) c0 (c127) c1 (c126) c126 (c1) c127 (c0) dio2 (dio1) v0 v0 v0 v0 v0 v4 v4 v4 v4 v4 v4 v4 v4 v4 v5 v5 v5 v5 v5 v1 v1 v1 v1 v1 v1 v1 v1 v1 frm t cl 01234 44454647 43 note: (1) clk is the clock from the rc-oscillator. (2) the frequency of both clk1 and clk2 is a half of the clk. t cl clk clk1 clk2 01 23 22
2005 mar 01 23 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 9 electrical characteristics 9.1 absolute maximum rating table 10 absolute maximum rating v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss, unless otherwise specified; t amb = ?2 0to+75 c notes 1. the following applies to the absolute maximum rating: a) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. b) the SBN6400G includes circuitry specifically designed for t he protection of its internal devices from the damaging effect of excessive static charge (esd ). however, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) parameters are valid over operating temp erature range, unless otherwise specified. d) all voltages are with respect to v ss, unless otherwise noted. 2. the condition v dd (v0) v1 v2 v3 v4 v5 must always be met. 3. qfp-type packages are sensitive to moisture of the env ironment, please check the drypack indicator on the tray package before soldering. exposure to moisture longer t han the rated drypack level may lead to cracking of the plastic package or broken bonding wiring inside the chip. symbol parameter min. max. unit v dd voltage on the v dd pin(pad) ? 0.3 +7.0 volts v ee negative voltage on the v ee pin(pad) v dd -16 volts v lcd (note 2) lcd bias voltage, v lcd =v0-v5 13 volts v i input voltage on any pin with respect to v ss ? 0.3 v dd +0.3 volts p d power dissipation 200 mw t stg storage temperature range ? 55 +125 c t amb operating ambient temperature range -30 + 85 c tsol (note 3) soldering temperature/time at pin 260 c, 10 second
2005 mar 01 24 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 10 dc characteristics table 11 dc characteristics v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss, unless otherwise specified; t amb = ?2 0to+75 c. notes: 1. lcd bias voltage v lcd is v0 - v5. v0 should always be connected to vdd. 2. for all input pins (pads), fs, ds1, ds2, cr, shl, ms, and psel. also, for all i/os, dio1, dio2, m, and cl when they are used as inputs. 3. for all output pins (pads), clk1, clk2, and frm. also, fo r all i/os, dio1, dio2, m, and cl when they are used as outputs 4. conditions for the measurement: cr=v dd , measured at the v dd pin. 5. this value is measured at the v dd pin (pad). the condition for t he measurement is as follows: a) r f =33k, c f =20 pf, b) display duty cycle=1/128 (ds1=ds2=1), c) master mode (m/s =1), and fs=shl=psel=1, and d) com0~com63 were left open. 6. this value is measured at the v dd pin (pad). the condition for t he measurement is as follows: a) display duty cycle=1/128 (ds1 =ds2=1), slave mode (m/s =0), and fs=shl=psel=cr=1, b) cl, m, and dio1 ar e from the master, and c) com0~com63 were left open. 7. the condition for the measurement is t he same as those described in note 5, except that the value is measured at the v ee pin(pad). 8. this measurement is for the tr ansmission high-voltage pmos or nmos of com0~com63. please refer to section 12, pin circuits, for detailed schematic of these drivers. the measurement is for the case when the voltage differential between the source and the drain of the high voltage pmos or nmos is 0.1 volts. symbol parameter condition min. typ. max. unit v dd supply voltage for logic 2.7 5.0 5.5 v v lcd lcd bias voltage v lcd = v0(v dd) -v5 note 1. 13 v v neg v neg =v dd -v ee 16 v v il low level input voltage note 2. 0 0.8 v v ih high level input voltage note 2. v dd -2.2 v dd v v ol low level output voltage of output terminals, at i ol =1.6 ma. note 3 0.0 0.3 v v oh high level output voltage of output terminals, at i oh =-200 a. note 3. v dd ? 0.3 v dd v i lkg leakage current of input pins(pads) for all inputs 0.2 a i stby standby current at v dd =5 volts note 4 3.0 a i dd(1) operating current for master mode with 1/128 display duty cycle note 5 960 a i dd(2) operating current for slave mode with 1/128 display duty cycle note 6 180 a i ee operating current measured at the v ee pin(pad) note 7 90 a c in input capacitance of all input pins 5.0 8.0 pf r on lcd driver on resistance note 8 1.5 ?
2005 mar 01 25 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 11 ac timing characteristics 11.1 clk1, clk2 timing for master mode table 12 clk1 and clk2 timing characteristics for master mode v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise specified; t amb = ?2 0to+75 c. symbol parameter conditions min. typ. max. unit t wh1 clk1 clock high pulse width 2000 ns t wl1 clk1 cock low pulse width 600 t r1 clk1 clock rise time 130 t f1 clk1 clock fall time 130 t wh2 clk2 clock high pulse width 2000 t wl2 clk2 clock low pulse width 600 t r2 clk2 clock rise time 130 t f2 clk2 clock fall time 130 t d12 clk1-to-clk2 delay 660 t d21 clk2-to-clk1 delay 660 fig.14 clk1 and clk2 timing for master mode 0.8vdd 0.2vdd 0.8vdd 0.8vdd 0.8vdd 0.8vdd 0.2vdd 0.2vdd 0.2vdd 0.8vdd clk1 clk2 t wh1 t wh2 t wl2 t wl1 t d12 t d21 t f1 t f2 t r1 t r2
2005 mar 01 26 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 11.2 cl, frm, dio1, dio2 and m timing for master mode table 13 cl, frm, dio1, dio2, and m timing for master mode v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise specified; t amb = ?2 0to+75 c. note: the measurement is with the load circuit connected for output terminals. the load circuit is shown in fig. 16. symbol parameter conditions min. typ. max. unit t whcl cl clock high pulse width 33 s t wlcl cl cock low pulse width 33 s t ds dio1 setup time (for shl=1), dio2 setup time (for shl=0) 18 s t dh dio1 hold time (for shl=1), dio2 hold time (for shl=0) 38 s t dd data delay time 4.6 s t dfrm frm delay time -1.8 +1.8 s t m m delay time -1.8 +1.8 s fig.15 cl, frm, dio1, dio2, and m timing when in master mode 0.8 x v dd cl dio1 (shl=v dd ) dio2, dio1 frm m (input of slave) (output of master) t dfrm 0.2 x v dd 0.8 x v dd 0.8 x v dd 0.8 x v dd 0.2 x v dd 0.8 x v dd t dd 0.8 x v dd t wlcl t ds t whcl t dm 0.8 x v dd 0.2 x v dd 0.2 x v dd t dfrm 0.8 x v dd 0.2 x v dd 0.2 x v dd t dd t dh start of a new frame t ds note: (1) psel=1, m/s =1 (2) c f =20 pf, r f =33k ohm. dio2 (shl=v ss )
2005 mar 01 27 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics fig.16 load circuit for timing diagrams. vss c l note: c l = 30 pf (including wiring and probe capacitance). pin
2005 mar 01 28 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 11.3 slave mode timing for 1/ 64 display duty cycle(ds1=l, ds2=h, shl=h(l), psel=l) fig.17 slave mode timing for 1/64 display duty 12 0 61 62 63 0 1 2 61 62 63 cl m dio1 (dio2) c0 (c63) c1 (c62) c62 (c1) c63 (c0) dio2 (dio1) note (1) psel=l. (2) shl=h. (3) if shl=l, then common output sequence is inverted, as shown in the parenthesis. v0 v0 v0 v0 v0 v4 v4 v4 v4 v4 v4 v4 v4 v4 v5 v5 v5 v5 v5 v1 v1 v1 v1 v1 v1 v1 v1 v1
2005 mar 01 29 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 12 pin circuits table 14 mos-level schematics of al l input, output, and i/o pins. symbol input/ output circuit notes clk1, clk2, fr outputs the output pmos and nmos also act as esd-protection devices. their sizes have been enlarged to increase esd protection voltage. ds1, ds2, fs, shl, psel, m/s input c, r, cr inputs for the pin electronics of the thes e inputs, please refer to fig. 5, section 4.1, on-chip rc oscillator. dio1, dio2, m, cl i/o the output pmos and nmos also act as esd-protection devices. their sizes have been enlarged to increase esd protection voltage. vss vdd pmos nmos vss vdd vss vdd data out output enable data in pmos nmos
2005 mar 01 30 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics com0~63, v0r, v0l, v1r, v1l, v4r, v4l, v5r, v5l symbol input/ output circuit notes com0~com63 v0r/v0l v1r/v1l v4r/v4l v5r/v5l v ee vdd en1 en2 en3 en4 vdd vdd vdd v ee v ee v ee v ee vdd
2005 mar 01 31 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 13 application notes 1. it is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. as the ics are fabricated in cmos and there is intrinsic latch-up problem associated with any cmos devices, proper power-up sequence can reduce the danger of triggering latch-up. w hen powering up the system, control logic power must be powered on first. when powering down the system, c ontrol logic must be shut off later than or at the same time with the lcd bias (v ee ). 2. the metal frame of the lcd panel should be grounded. 3. a 0.1 f ceramic capacitor should be connected between v dd and v ss . 4. a 0.1 f ceramic capacitor should be connected between v dd (or v ss ) and each of v1, v2, v3, v4, and v5. v dd signal v ee 5v 0v -11v 0~50 ms 1 second (minimum) 0 second 0 second (minimum) (minimum) 0~50 ms 1 second (minimum) fig.18 recommended power up/down sequence
2005 mar 01 32 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 14 package information package information is provided in another document. please contact avant electronics for package information.
2005 mar 01 33 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 15 soldering 15.1 introduction there is no soldering method that is i deal for all ic packages. wave solderi ng is often preferred when through-hole and surface mounted components are mixed on one printed-circuit boar d. however, wave soldering is not always suitable for surface mounted ics, or for printed-circui ts with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. for more in-depth account of so ldering ics, please refer to dedicated reference materials. 15.2 reflow soldering reflow soldering techniques ar e suitable for all qfp packages. the choice of heating method may be influenced by larger plasti c qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutel y dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can c ause cracking of the plastic body. for more information, please contact avant for drypack information. reflow soldering requires solder paste (a suspension of fine solder particles, flux and bind ing agent) to be applied to the printed-circuit board by screen printi ng, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, t hermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typica l reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating dur ation: 45 minutes at 45 c. 15.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of inco mplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, th e following conditions must be observed: ? a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. ? the footprint must be at an angle of 45 to the board direction and mu st incorporate solder thieves downstream and at the side corners. during placement and before so ldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of pack age immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 repairing so ldered joints fix the component by first soldering two diagonally- opposit e end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2005 mar 01 34 of 34 data sheet (v2) 64-common driver for dot-matrix stn lcd SBN6400G avant electronics 16 life support applications avant?s products, unless specifically specified, are not des igned for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. avant customers using or selling avant?s products for use in such applications do so at their own risk and agree to fully indemnify avant for any damages resulting from such improper use or sale.

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